FinFET and other MOS transistors are susceptible to damage through electrostatic discharge caused by various different components that combine to form an integrated circuit or other semiconductor device. It is naturally desirable to prevent any ESD damage and to raise the level of current at which ESD failure occurs so that the transistors are less susceptible to ESD damage and have increased functionality.
For MOS transistors that do not utilize silicide block contacts to drain, the ESD current, i.e. the current propagated through electrostatic discharge, may become concentrated in surface areas such as in the light doped drain (LDD) portion of a device disposed between the primary source/drain and the transistor gate. This can cause local heating and can undesirably induce a transistor to turn on in response to conditions that are not intended to turn the transistor on. In particular, the current propagated through electrostatic discharge can undesirably induce a transistor to turn on at lower applied voltage levels than desired. It is often desirable to have all transistors in an array turn on at the same voltage/current conditions. Some previous approaches at addressing this issue, i.e. raising the ESD failure current, It2, have been to add silicide blocks, but this requires extending the distance between the drain and the gate and undesirably requires additional space on the chip. When transistors turn on in conditions not intended for the transistors to turn on, device failure can occur.